Xilinx Field Programmable Gate Array, Part #: XA7S50-2CSGA324I | FPGA | DEX Medical Gloves The Arm Cortex-M3 CPU incorporates

The Arm Cortex-M3 CPU incorporates a 3-stage pipeline and uses a Harvard architecture with separate local instruction and data buses as well as a third bus for peripherals

ITL:CM8068404404932S RGQX

40°C to +125°C

Xilinx FPGA Part #XC7Z020-1CLG400I

Xilinx Field Programmable Gate Array, Part #: XA7S50-2CSGA324I | FPGA | DEX Medical Gloves The Arm Cortex-M3 CPU incorporatesXilinx FPGA XA7S50 2CSGA324I is optimized for 1. 8V systems Industrys fastest low power CPLD Densities from 32 to 512 macrocells Industrys best 0. 18 micron CMOS CPLD Optimized architecture for effective logic synthesis Multi voltage I O operation 1. 5V to 3. 3V Advanced system features Fastest in system programming 1. 8V ISP using IEEE 1532 (JTAG) interface On The Fly Reconfiguration (OTF) IEEE1149. 1 JTAG Boundary Scan Test Optional Schmitt trigger